1. Field of Invention
The present invention relates to eliminating glitches caused by clock switching, more particularly, to a circuit design used in a delay-locked loop (DLL) to eliminate glitches for clock outputs and a method that prevents glitches of a variable delay clock selected from a plurality of clock delay lines.
2. Related Art
Clock signals are the synchronization basis of a digital logic circuit. Different logic operations will be concurrently performed at each transition of the clock. Therefore, the operation results of the digital logic circuit will not be predictable if those logic operations cannot concurrently performed at the transitions.
In digital circuit designs, clock signals are always spread to many logic units, such as an adder, a subtracter, a multiplier, a multiplexer, and a shifter. However, when the signal lines are too long, different receiving ends of the signal lines may have many different phases with respect to the original clock signal source from the clock generator. Thus, the logic units cannot perform operations at the same time, resulting in unpredictable results. To solve the problem caused by clock delays, a DLL is utilized to minimize the clock phase differences, so that each logic unit can perform operations at the same time.
With reference to FIG. 1, in the clock output circuit of a DLL in the prior art, the input signal CNT can be used to switch different clock delay lines CLK_N, CLK_N+1 to an output signal CLKO in response to an input signal CNT through a selection circuit 1, so that the output signal CLKO is a variable delayed clock signal. When the input signal CNT is N, only the select signal SEL_N output from the selection circuit 1 is High, while the other select signals are Low. The clock delay line CLK_N passes through an AND gate 2 and an OR gate 4 to generate the output signal CLKO. When the input signal CNT is N+1, only the select signal SEL_N+1 output from the selection circuit 1 is High, while the other select signals are Low. The clock delay line CLK_N+1 passes through an AND gate 3 and an OR gate 4 to generate the output signal CLKO accordingly.
When the input signal CNT transits from N to N+1 or from N+1 to N, if the transition time falls within the clock delay interval or phase difference of the delay lines CLK_N and CLK_N+1, then glitches 5 will happen in the output signal CLKO, as shown in FIGS. 2A and 2B. In other words, the select signals SEL_N and SEL_N+1 in the selection circuit 1 are switched within the clock delay interval or phase difference of the clock delay lines CLK_N and CLK_N+1. Glitches will cause problems in the output signal CLKO. Such a clock with glitches will fail the logic circuit . The invention provides a circuit and method that eliminate glitches in a DLL during clock switching.
A primary objective of the invention is to provide a circuit and method that eliminate the glitches in the clock output circuit of a DLL (Delay-Locked Loop) by adaptively delaying the switching time of the select signal.
Another objective of the invention is to provide a method that generates a variable delay clock. The method selects from a plurality of clock delay lines to send out an output signal without glitches by delaying the switching time.
A further objective of the invention is to provide a circuit and method that utilize the rising edge or the falling edge of the clock of the clock delay line as the switching time of a variable delay clock in the clock output circuit of a DLL.
In view of the problem that generating glitches at the select signal switching time by the clock output signal may cause digital modules or systems to have incorrect operations, the invention provides a clock output circuit and a method for generating a variable delay clock in a DLL. The clock rising edge or the clock falling edge of the clock delay line is utilized as the switching time of the variable delay clock to eliminate the glitches in the clock output signal.
In an embodiment of the invention, the DLL clock output circuit contains a selection circuit. A plurality of select signals switch the corresponding clock delay lines to the output signal, wherein each select signal properly delays the time point which the select signal switches the clock delay line to the output signal by passing through a delay switching circuit, so as to produce a variable delayed clock signal without glitches.